1. Field of the Invention
The present invention relates to a driver circuit configured to transmit an electric signal.
2. Description of the Related Art
In order to transmit pulse signals, or signals similar to pulse signals, to a separate circuit via a propagation path, a driver circuit is employed. In recent years, with improved high-speed semiconductor devices, such driver circuits are also required to perform high-speed operations. In order to improve the operation speed of such driver circuits, various approaches have been proposed as follows.
FIGS. 1A and 1B are a circuit diagram showing an example configuration of a high-speed driver circuit and a time chart showing the operation thereof, respectively.
A driver circuit 200 shown in FIG. 1A includes a transistor Q1, a constant current circuit 202, and a capacitor C1. A capacitor C2 represents a parasitic capacitance of the emitter of the transistor Q1 and a parasitic capacitance of a wiring line.
The transistor Q1 and the constant current circuit 202 form a so-called emitter follower circuit. The transistor Q1 is configured as an NPN bipolar transistor, and the capacitor C1 is arranged between the base of the transistor Q1 and the emitter thereof. It should be noted that the transistor Q1 may be configured as a PNP bipolar transistor. Alternatively, the transistor Q1 may be configured as an N-channel FET (Field Effect Transistor) or a P-channel FET.
In order to enable such a driver circuit (emitter follower) 200 to perform high-speed operations, the constant current circuit 202 should be designed to generate a large current I2. However, this increases constant current consumption, which is undesirable. Accordingly, the capacitor C1 is arranged in order to suppress current consumption while improving the slew rate.
Starting from the top and in the following order, the waveform diagrams shown in FIG. 1B illustrate: the input voltage Vin, the output voltage Vout, and the charge/discharge current I1 that flows to/from the capacitor C1. In the waveform diagram of the output voltage Vout, the dotted line represents the waveform of the output voltage Vout in a case in which the capacitor C1 is not provided, and the solid line represents the waveform of the output voltage Vout in a case in which the capacitor C1 is provided. Such an arrangement employing the capacitor C1 as an additional component allows the charge stored in the capacitor C2 to be discharged via the capacitor C1, in addition to the constant current circuit 202. Thus, such an arrangement provides the improved slew rate.
However, in order to provide a capacitor C1 having high speed charging and discharging, there is a need to provide a circuit having high driving power (low output impedance) as an upstream component of the driver circuit 200, leading to reduction in the range of application.
FIGS. 2A and 2B are a circuit diagram showing another example configuration of a high-speed driver circuit and a time chart showing the operation thereof, respectively.
A driver circuit 300 shown in FIG. 2A includes a transistor Q2, a constant current circuit 302, and a capacitor C3. A capacitor C4 represents a parasitic capacitance that occurs at the transistors Q2 and Q3, the wiring lines, and so forth.
A constant current circuit 302 is configured as a so-called current mirror circuit. The current mirror circuit includes transistors Q3 and Q4, and resistors R1 and R2. A constant current Ic is supplied to the input side of the current mirror circuit, and a current I4 is output from the output side thereof. A capacitor C3 is arranged between an input terminal Pin of the driver circuit 300 and a connection node that connects the transistor Q4 and the resistor R1.
Starting from the top and in the following order, the waveform diagrams shown in FIG. 2B illustrate: the input voltage Vin, the output voltage Vout, the charge/discharge current I3 that flows to/from the capacitor C3, and the output current I4 of the constant current circuit 302. In the waveform diagram of the output voltage Vout, the dotted line represents the output voltage Vout in a case in which the capacitor C3 is not provided, and the solid line represents the output voltage Vout in a case in which the capacitor C3 is provided. Such an arrangement employing the capacitor C3 as an additional component improves the slew rate. Furthermore, the voltage change that occurs at the resistor R1 due to the current component that flows through the capacitor C3 is superimposed on the emitter voltage V1. Thus, such an arrangement can provide a large change in the output current I4 of the constant current circuit 302.
However, if the emitter voltage V1 of the transistor Q4 is greater than the base voltage thereof, the current change speed is reduced. Accordingly, the maximum value of the output current I4 is limited to twice the value of the state (steady state) when there is no edge (level transition). This leads to a problem in that a limit is placed on the slew rate.